1. Field of the Invention
The invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device comprising two transistors and one capacitor in an equivalent circuit.
2. Description of the Related Art
A hitherto known RAM with a simplest structure comprises one transistor and one capacitor and is designed to turn on and off the gate by means of the transistor to change the amount of charges of the capacitor, thereby storing information in desired memory cells.
FIG. 11 is a plane view showing RAM having 2 unit cells, each of which includes one transistor and one capacitor. FIG. 12 is a sectional view taken from line 12--12 of FIG. 11 showing the RAM which has the capacitor comprising lower and upper electrodes sandwiching therebetween a ferroelectric film of higher dielectric constant for achieving a larger capacity per unit area. In detail, a silicon substrate 1 is provided with a device-isolating region 12 to possess a device-forming region wherein a gate electrode 5 having side walls 6 and a protective film 7 is formed on the silicon substrate 1 through a gate oxide film 4 to behave as a word line, a source/drain region 3 extends on the surface of the silicon substrate 1 at both sides of the gate electrode 5, a capacitor lower electrode 64 having contact with the source/drain region 3 is layered above the gate electrode 5, source/drain region 3 and device-isolating region 12 through a dielectric film 8, a capacitor upper electrode 65 is layered on the lower electrode 64 through a ferroelectric film 66, an interlayer dielectric film 67 is deposited on the capacitor upper electrode 65, and a bit line 60 is connected to another part of source/drain region 3 opposite to that having contact with the capacitor electrode 64.
Next, operation of the RAM will be detailed with referring to FIG. 13.
The side having the upper electrode 65 opposite to the bit line (B) is first set to have electric potential of Vcc/2(V) before writing information. The bit line (B) is applied with Vcc(V) for writing "1" and with 0 (V) for writing "0" as shown in FIGS. 13(a) and 13(b). Residual polarization charges are stored in the capacitor with orientation of polarization being reversed as seen.
Also, for reading information, the side having the upper electrode 65 is first set to have electric potential of Vcc/2(V) and the bit line (B) is applied with Vcc(V). In reading "1", orientation of polarization of the capacitor is not reversed but the same as that in writing "1" as seen in FIGS. 13(a) and 13(c) to allow a flow of electric charge represented by the formula I=(Ps-Pr)/.DELTA.t where Ps is saturated polarization charges, Pr residual polarization charges and .DELTA.t reversing rates. In reading "0", orientation of polarization of the capacitor is reversed to that in writing "0" as shown in FIGS. 13(b) and 13(d) to largely change the amount of charges to a higher flow thereof as I={2Pr+(Ps-Pr)}/.DELTA.t=(Pr+Ps)/.DELTA.t than that in reading "1". Hence, "1" and "0" are read and determined in view of specific flow of the electric charges.
The above semiconductor memory device needs to enlarge capacity of the capacitor for keeping charges to be stored therein. Enlargement of capacity of the capacitor in the memory cell is inconsistent with decrease of sizes of the memory cell, leading to such a problem or task that various contrivances are used for reducing sizes of the memory cell.
There is also a problem wherein the capacitor upper and lower electrodes 64, 65 are positioned lower than and do not extend outward with respect to the bit line 60 as seen in FIG. 12, so that areas of the upper and lower electrodes 64, 65 in the memory cell are limited by the bit line 60 and a reversed bit line (not shown).
There is a further problem that the memory cell in which reading is carried out by determining specific flow of electric charges requires a dummy cell for the reading operation, so that the reading rate is limited.
The present invention has been designed to overcome the above problems. An object of the invention is to provide a reliable semiconductor memory device in which a circuit and structure of memory cell is simplified to achieve a larger capacity of the capacitor and reading can be carried out at a higher reading rate without use of a dummy cell.